Joel Emer is a Senior Distinguished Research Scientist at Nvidia and a Professor of the Practice at MIT. His research area is computer architecture, where he is known as a developer of the widely-employed quantitative approach to processor performance evaluation, and recognized for his pioneering contributions to simultaneous multithreading, processor reliability analysis, cache organization, pipelined processor organization and spatial architectures for deep learning. He contributed to several VAX, Alpha, and X86 processors. His awards include the Eckert-Mauchly Award for lifetime contributions in computer architecture. He is a fellow of the IEEE and ACM and member of the NAE.