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Summer Bridge on Critical Materials
June 15, 2024 Volume 54 Issue 2
The summer issue of The Bridge discusses leveraging new and emerging technologies, infrastructure, innovative approaches, and a resilient supply chain to ensure a stable and reliable supply of critical materials far into the future.

Critical Needs for Non-PFAS Semiconductor Packaging Materials

Wednesday, June 12, 2024

Author: Pradeep Lall

There is a critical need for research on and development of new non-PFAS materials.

Environmental, social, and governance factors are used to evaluate companies to gauge their level of advancement with regards to sustainability. Sustainability has received increased attention owing to growing awareness of global environmental impact and the migration of the financial industry towards using environmental, social, and governance factors in assessing future growth potential and investment decisions. Presently, the semiconductor industry relies on per- and poly-fluoroalkyl substances (PFAS), a group of over four thousand man-made chemicals used in various consumer electronics. PFAS materials have shown the propensity to get into the water supply, linking those materials to a range of health concerns.

There is a critical need for non-PFAS material replacements that can provide similar or better properties in comparison with the PFAS counterparts presently in use.

There is a renewed focus in several application areas on eliminating and finding suitable replacements for existing PFAS material sets. Environmental regulations seek to limit PFAS use in electronics and are divided into two types (Acquis 2023): (1) Reportable PFAS regulations that pertain to PFAS inten­tionally added during electronics manufacturing processes. EU REACH (­Registration, ­Evaluation, Authorization, and Restriction of Chemicals) and the state of Maine in the United States, under the Toxic Substances Control Act, apply specific reporting requirements for reportable PFAS. (2) Restricted PFAS include long-chain PFAS, such as perfluorooctanoic acid, which are categorized as being persistent and toxic. Regulations, such as EU Persistent Organic ­Pollutants and REACH Annex XVII Entry 65, aim to limit the use of restricted PFAS in electronics. There is a critical need for non-PFAS material replacements that can provide similar or better properties in comparison with the PFAS counterparts presently in use. In this article, the role of PFAS in semiconductor package components is discussed, along with the specific performance enhancements enabled by PFAS for each function.

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The Role of Semiconductor Packaging

Bare chips require packaging in order to fulfill a number of critical functions, including environmental protection, thermal management, power delivery, fan-out of the chip pitch for compatibility with the coarser pitch of printed circuit board technologies, and elimination of the need for a high-grade cleanroom for the pick-n-place part assembly on the printed circuit boards. The device packaging can take a number of forms depending on the product architecture. The main components in a semi­conductor package are the package substrate, the silicon chip-to-­substrate interconnects, the substrate to the ­printed ­circuit board (PCB) interconnects, die-attach, underfills, and overmolds or lids. The silicon chip-to-substrate interconnects are called the first-level inter­connects, and the ­substrate-to-PCB interconnects are often referred to as the second-level interconnects. The functions of these package elements include:

    Package Substrate: The package substrate performs the function of fan-out of the fine-pitch chip interconnects to the coarse pitch of the printed circuit board. Substrates may be made of organic laminates or ceramic, depending on the application. Organic laminates are composites consisting of epoxy-impregnated glass fibers. Substrates are generally multilayer and use high-density interconnect wiring compared to printed circuit boards.

    Si Chip-to-Substrate Interconnects: The chip can be inter­connected to the substrate using a variety of ­inter­connects, including flip-chip solder bumps, wire bonds, or tape-automated bonding. Most modern high-performance packaging uses flip-chip solder bumps, while packaging with lower I/O counts uses predominantly wire bonds for interconnection. Flip-chip solder bumps are typically formed from solder bumps termed C4 bumps or controlled collapse chip connections.

    Substrate-to-PCB Interconnects: The semiconductor package can be interconnected to the printed circuit board with balls, columns, leads, or no-lead terminations, depending on the package format. Solder is the predominant material used to connect the package interconnects to the printed circuit board. The solder may have fluxes in the formulation for the wetting ­processes during reflow and assembly.

    Die-Attach: The chip is attached to the substrate for wire-bond configurations using a chip-attach or die-attach material dispensed on the substrate or the lead frame. The die-attach is also designed to accommodate the thermal mismatch between the silicon chip and the substrate or the lead frame and to provide a thermal heat dissipation path from the chip to the printed circuit board.

    Underfills: The gap between the chip and the substrate may be reinforced with underfills to provide supplemental reinforcement for the first-level interconnects and accommodate the differential thermal expansion between the chip and the substrate during thermal or power cycling. Underfills are required to bond to the chip and solder mask of the substrate in addition to encapsulating the first-level interconnects.

    Overmolds or Lids: Plastic-encapsulated micro­electronics packages use overmolds to protect the chip and provide ease of handling. Epoxy mold compounds, which are composites of epoxy and filler particles, are used to provide encapsulation of the chip and the inter­connects. Lids are used in some applications that require high-temperature operation or higher heat dissipation. Common materials include copper or aluminum lids for attachment to heat sinks.

Semiconductor Packaging Formats

Earlier electronic architectures used through-hole packaging to interconnect the semiconductor packages to the printed circuit boards. The packages were interconnected by inserting the package leads into through holes in the PCB. The current generation of semiconductor packaging predominantly uses a surface mount format in which the second-level interconnects are attached to the surface of the printed circuit board. Some applications may have packages with copper lands that are connected to socket contacts. The sockets may themselves be mounted on the printed circuit board. The surface-mount packaging architectures may be broadly categorized into area-array, leaded, and leadless packages. Area-array and leaded architectures may use balls, columns, or punch-and-form leads (figure 1). Some examples of leaded, leadless, and area-array packaging architectures are listed below:

    Area-array packaging: plastic ball grid arrays, flip-chip ball grid arrays, ceramic ball grid arrays, ceramic column grid arrays, wafer-level chip scale package, fan-out wafer-level package.

    Leaded packaging: thin-small outline package, small outline integrated circuit, flip-chip small outline package, quad flat pack.

    Leadless packaging: quad flat no-lead, metal lead frame, leadless chip carrier, ceramic leadless chip carrier.

Functions Enabled by PFAS Materials

Semiconductor packaging involves the use of different materials throughout various process steps, each requiring specific material properties and quality characteristics (table 1). PFAS are known for their thermal and chemical stability. They also provide electrical properties such as low dielectric constant and loss, which are essential for high-speed and high-bandwidth communication. There are several other noteworthy properties of PFAS, including their thermal and chemical resistance, low dielectric constant, low residue transfer, improvement of surface wetting, and photo imageability. These properties help increase yield quality and reliability and enable the multi-step processing required for complex packaging designs of the future. It’s worth noting that PFAS have not yet been classified as regulated materials in semiconductor packaging.

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Substrate Core and Buildup Layers

PFAS materials enable a number of required properties in substrate materials, including low permittivity (low-k, er), low dielectric loss, low water absorption, and low ­coefficient of thermal expansion (CTE) (Elsherbini et al. 2022; Jiangxi Tieno Technology Co. Ltd. 2019; Shantou Ultrasonic 2019; Taiwan Semiconductor Manufacturing Co. TSMC Ltd. 2019). PFAS in buildup (or dielectric) materials within the substrate enables low-k, low dielectric loss, low water absorption, low CTE or CTE matching, high strength adhesion, improved dimensional stability, compliance or modulus matching, and reliability (Japp et al. 2008; Starkston et al. 2021; Wu C-W et al. 2017). Fluorinated materials allow for high glass transition temperatures, ensuring the material remains rigid at elevated operating temperatures. Dielectric loss is a measure of the electromagnetic energy absorbed by the material. The substrate core may be required to operate in a wide electromagnetic frequency range at low ­voltages, making the low absorption of electromagnetic energy important for maintaining signal fidelity. Environmental exposure of electronics to moisture often results in water absorption into the substrate core and buildup ­layers of the semi­conductor package, which can dramatically affect the dielectric properties of the substrate owing to the significantly different dielectric properties of water. CTE is a measure of the dimensional change realized per unit change in temperature. During operation, semiconductor packaging dissipates heat, resulting in the formation of temperature gradients in the structure. Large differences in the CTE of the buildup layers with the conductive ­traces and other semiconductor packaging materials result in warpage or loss of coplanarity. Low warpage is needed to prevent failure of electrical inter­connects, cratering, de-adhesion, or material fatigue. ­Fluorinated polymers like polytetrafluoroethylene (PTFE), or ­Teflon, and related materials have low CTE, making them desirable for use in buildup layers and in the core of the semi­conductor package substrates. Commercially available fluorinated buildup materials include Teflon, Teflon-FEP, Teflon-PFA, Teflon-AF, Teflon-PTFE-30, Tefzel, Halar, KEL-F, HBF-430, and Zonyl PTFE TE-3667N.


Fluxes in semiconductor packaging exist in conjunction with solders and solder paste used in chip and component assembly. Reflow during assembly typically has a ramp and soak in the time-temperature profile to allow time for flux activation and wetting. PFAS materials are used in fluxes to perform the functions of diluent vehicles or media (Cole 1981), cleaning agents (Hori et al. 2019), base resins (Arakawa Chemical Industries Ltd. 2013), and surfactants (Freescale ­Semiconductor, Inc. 2010; International Business Machines Corp 1973). PFAS in flux-surfactants provides the material the properties of increased heat resistance, wetting, and spreading of solder on the conductive surfaces. Flux is typically applied to the substrate prior to chip pick-and-place and reflow to allow for removal of the surface oxides. The time-­temperature profile of the reflow process is ­intended to interact with the flux to allow sufficient time for activation of the flux prior to the liquidus zone. PFAS in fluxes are used to promote temperature stability during flux activation, prevent pre-mature flux-degradation or residue formation, and prevent voiding. Excessive solder joint voiding has been shown to degrade reliability (Arakawa Chemical Industries Ltd. 2013). Increased residue formation has been shown to degrade insulation resistance during the operation of electronics in extreme environments.

Die-Attach or Chip-Attach Adhesives

Chip-attach adhesives, also known as die-attach ­adhesives, serve the purpose of mounting semiconductors or silicon chips to package substrates or lead frames. These ­adhesives form a strong attachment and help reduce stress and control warpage during the system’s operation. For semi­conductors used in power management, computation, or dynamic random access memory, die-attach adhesives with a high heat transfer coefficient, low ­coefficient of thermal expansion, and resistance to ­thermal fatigue are required due to the significant amount of heat generated during operation. To achieve efficient heat transfer away from the semiconductor die, fluorinated polymers are currently used as a constituent in the die-attach adhesive, as they possess low CTE and resistance to thermal fatigue, making them ideal for enabling a high heat-transfer co­efficient, low CTE, and resistance to thermal fatigue. PTFE is an essential component in certain die-attach adhesives that are used to manage the flow and bleeding of the ­adhesive during polymerization. The PTFE “antibleed agents” play a critical role in regulating the amount of epoxy bleed beyond the die mounted to the lead frame substrate to prevent it from spreading to other critical areas, such as wire bond pads. This is crucial because such spreading can result in product failures like wire non-stick on pads and prevent mold compound adhesion, which can lead to void and delamination on the package. In addition, PTFE helps to promote flatness of the die and uniform adhesive thickness (Marks et al. 1994; Zhang et al. 2017). Some die-attach pastes, encapsulants, and underfill materials utilize PFAS-containing chemicals as efficient surfactant agents that adjust surface energy with a low level of less than 0.1% in total weight to meet performance requirements for semiconductor applications.

Release Layer

The chip is in wafer form prior to backgrinding and being diced into individual chips for assembly into the semiconductor package. For the dicing operation, the wafer is mounted on a frame with a tape backing, also called the carrier tape or backgrinding tape depending on the operation for which the tape is used. The tapes have adhesive layers to secure the wafer to the tape. The adhesive provides the adhesion to the wafer but also may have underlying release layers for the removal of the chips through thermal, laser, mechanical, or a combination of mechanisms. Fluorinated polymers are used for anti-adhesion or release layers for carrier and back­grinding tapes (Schelcher et al. 2011). Fluorinated polymers are also used to form laser-release layers, relying on the UV sensitivity of the PFAS materials. Release layers and pressure-sensitive adhesives rely on the use of fluorinated materials to prevent the adhesion between the overlying adhesive and the underlying film of the carrier tape or the backgrinding tape (Nitto Denko Co. 2018). PFAS materials are also used as drip inhibitors during wafer processing (Inazawa and Ishada 2017).

The impact of the elimination of PFAS on packaging performance, material stability, consistency, and suitability for the application relative to the PFAS counterparts is relatively unknown.

Electronic Mold Compounds

The silicon chip is generally encapsulated using an electronic mold compound (EMC). The encapsulation is accomplished using an injection molding process or using glop-top dispense. Once molded, the part needs to be ejected from the mold for post-mold lead-forming operations for leaded parts or singulation for organic laminate parts. PFAS materials are used in liquid or film form as mold releases agents for a clean mold release while enabling thermal stability. Ethylene tetrafluoroethylene and PTFE are used as mold release agents. Materials such as silicone contaminate other parts of the semi­conductor packaging process, tools, or packaging and delaminate downstream material additions. PFAS may be used as a catalyst for the cure of the epoxy mold compound. ­Sulfonic acids or boron trifluoride act as ion exchange resins. Fluoro compounds may be used in small percentages to thin the epoxy used for molding while maintaining the overall material characteristics (Nippon Shokubai Co. Ltd. 2013). In addition, PFAS materials are used to provide thermal stability and flame retardancy. PTFE is used to provide flame retardance (Inazawa and Ishada 2017; Teijin Ltd. 1999).


Underfills are supplemental restraints added to the semiconductor package to reinforce the interconnects after damage during normal operation or handling. The underfill materials are composites consisting of an epoxy matrix with silica filler particles. The volume fraction of the silica filler particles is used to control the coefficient of thermal expansion in addition to the elastic modulus of the composite. Filler percentages range from 50-60 percent for most commercial underfills. The epoxy matrix is designed to have high viscosity and low volatility. The high viscosity is preferred to ensure a homogenous filler distribution in the epoxy matrix and reduce void entrapment. Reduction in viscosity of the underfill during dispense can be achieved through exposure to temperature or through shear thinning. Underfills are used to increase the semiconductor package reliability. The underfills are used in conjunction with the flip-chip joints in the gap between the silicon chip and the substrate or between the semiconductor package and the printed circuit board. Predominantly, three configurations are used for underfilling, including full underfill, corner underfill, and edge bonding. The full underfill configuration is used to completely fill the gap between the chip and substrate or between the package and PCB. The corner underfill involves dispensing the underfill in the corners of the package, while the edge underfill only involves underfilling the edges of the package. B-stage cured underfills may be dispensed as films on the surface of the chip, with the full cure achieved during the reflow and assembly process. Fluoro-propyl groups in the underfill are used to improve mechanical strength and reliability through the formation of a semi-solid film on the chip surface (Toray Industries Inc. 2018). Furthermore, stress relief of the solder interconnects may be achieved through the use of semi-solid fluorinated rubbers, including ­vinylidene fluoride-propylene hexafluoride copolymer and ­tetrafluoroethylene-propylene copolymer (NAMICS 2018). PFAS materials are used in underfills to prevent the formation of air bubbles or voids, improve high-­temperature performance, and prevent resin bleedout.

Thermal Interface Materials

Thermal interface materials (TIMs) are used to fill the asperities between the mating surfaces in a semi­conductor package to reduce the thermal resistance. The TIM layer needs to be tear-resistant with high tensile strength to prevent degradation during operation in which the semiconductor package is subjected to a sustained high temperature or wide temperature extremes. The addition of fillers is often used to control the conductivity of the thermal interface materials. PFAS materials such as fluorinated ethylene propylene provide unique compatibility for the incorporation of fillers, including carbon nano-tubes, metals, and ceramics, into thermal interface materials (Thomasset 2014). High thermal conductivity can be achieved through the use of fluorocarbon ­resins, fluoro resins, or fluorinated polyallyl ether resins. The materials enable compatibility, including adhesion to the constituents, in addition to providing the high ­viscosity and elasticity needed to sustain differential thermal expansion during power and environmental cycling (Cabot Corp 2016; Hermann 2012).


PFAS are widely used in the design and manufacture of semiconductor packaging. Critical functions provided by PFAS have been identified in the substrate core, substrate buildup layers, fluxes, adhesives, underfills, electronic mold compounds, and thermal interface materials. In each of the package components, PFAS in the present generation of electronics are used to perform a range of functions, including low permittivity, low dielectric loss, low coefficient of thermal expansion, mechanical strength, adhesion, chemical resistance, surfactants, dimensional ­stability, flame retardance, and thermal conductivity. There is a critical need for research on and development of new non-PFAS materials that provide the critical functions for each package component while ensuring reliable operation performance. A number of new non-PFAS materials have been put forth for some of the applications highlighted in this article. However, the materials and their reliability and performance are relatively unknown. Furthermore, the impact of the elimination of PFAS on packaging performance, material stability, consistency, and suitability for the application relative to the PFAS counterparts is ­relatively unknown. Reliability data is needed for representative use cases to mitigate the risks associated with the adoption of these materials into mission-critical applications.


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About the Author:Pradeep Lall is MacFarlane Endowed Distinguished Professor and alumni ­professor, Auburn University.